This invention relates to a method of fabrication of semiconductor integrated circuits, more particularly of bipolar semiconductor integrated circuits suitable for high levels of integration and high-speed operation.
High-speed semiconductor integrated circuits generally employ bipolar emitter-coupled logic or current-mode logic. To improve the speed of these devices, it is necessary to reduce the parasitic capacitance of their circuit elements and interconnection wiring, reduce the base resistance of their transistors, and increase the transistor gain-bandwidth product, i.e. the transistor cutoff frequency.
A major contribution to the parasitic capacitance is made by the capacitance of the base-collector junctions in the transistors. A widely-adopted scheme for reducing the parasitic capacitance is to reduce the area of these junctions by using a polysilicon lead to connect the base with an electrode out side the transistor area. An effective method of reducing the parasitic capacitance of the polysilicon resistors and metal interconnection wiring is to form these on a thick isolation oxide layer.
To reduce the base resistance, it is necessary to reduce the width of the emitter, reduce the resistance of the active base layer disposed thereunder, and bring the low-resistance passive base closer to the emitter. An effective way to improve the gain-bandwidth product is to reduce the depth of the emitter-base junction and reduce the thickness of the epitaxial layer in which the collector, emitter, and base are formed.
The foregoing measures have been taken in a prior-art fabrication method described in Japanese Laid-open Patent Application No. 290173/1987, comprising a first step for creating mutually isolated device regions on a P.sup.- silicon substrate, a second step for creating a first part of the passive base by medium-concentration boron ion implantation, a third step for creating polysilicon electrodes and resistors, a fourth step for implanting a high concentration of boron ions into the polysilicon base electrodes and the ends of the polysilicon resistors, a fifth step for implanting low-concentration boron ions into the polysilicon electrodes and resistors and diffusing the implanted boron ions into the underlying silicon to complete the formation of the base, a sixth step for opening contact holes, a seventh step for forming a thin oxide film on the polysilicon surface exposed in the contact holes, an eighth step for implanting arsenic ions through the thin oxide film into the polysilicon in the contact holes, a ninth step for diffusing the arsenic ions to form an emitter in the active base region, and a tenth step for metalization. This fabrication method creates fairly high-performance transistors having a reduced base area, a shallow baseemitter junction, and the other requisites mentioned above.
A problem in the method just described is that in the fourth step, the boron ions are implanted into the polysilicon through a comparatively thick protective oxide layer created by oxidizing the upper 1800 to 2000 angstroms of the polysilicon. A substantial percentage of the implanted ions is trapped in the oxide layer and does not reach the polysilicon. Accordingly, irregularities in the oxide thickness create substantial variations in the amount of boron actually implanted in the polysilicon; this leads to problems of nonuniformity and non-reproducibility of transistor characteristics and resistance values.
A related problem is that to allow for the thick oxidation, the original polysilicon layer must itself be thick, so that much time is needed for selectively oxidizing the polysilicon areas to create the electrodes and resistors in the third step. A result is that the original medium-concentration base is deepened and the epitaxial layer in which the base and collector are formed must be thick enough to accommodate this depth; both of these factors limit the improvement in the gain-bandwidth product. In addition, the extension of the medium-concentration base into the region below the emitter limits the reduction of the emitter width and reduction of the base resistance, enlarges the emitterbase capacitance, thereby limiting the transistor switching speed, and reduces the width of the active base, thereby limiting the current gain of the transistor. The long selective oxidation time furthermore allows oxidation to proceed in the horizontal direction and promotes the growth of "bird's-beaks," which in turn limits the fineness of the structures that can be realized.
Yet another problem is that the preceding method is not suitable for creating arsenic-doped polysilicon resistors with very low sheet resistance values.